1. Field of the Invention
This invention relates to improvements in a method of producing semiconductor devices upon using a resist mask to accomplish a plurality of ion implantations (employed, for example, in production of semiconductor memories such as CMOS and DRAM), more particularly to such a semiconductor device production method in which the number of steps for forming resist masks can be considerably reduced by virtue of using an oblique ion implantation through a relatively small opening portion formed in the resist mask.
2. Description of the Related Art
Hitherto a variety of production methods for semiconductor devices have been proposed and put into practical use. In a typical one of them, in order to form a well, a channel stop or the like in a semiconductor substrate, a region different in conductivity type from the well is wholly covered with a resist mask, upon which ion implantation is carried out. Additionally in order to form a source and a drain in the well, another resist mask is newly patterned, upon which a high concentration doping is carried out. The reason why the resist mask is thus changed is that a connected section (high concentration impurity layer) is formed in the region different in conductivity from the well simultaneously with the formation of the source drain under an ion implantation. The connected section is for potential fixture.
Such a production method of the semiconductor device will be discussed with reference to FIGS. 6A to 8C.
First, as shown in FIG. 6A, LOCOS oxide films 2A, 2B are formed at an element separation region of the surface of a N-type silicon substrate by using a known selective oxidizing technique. The LOCOS oxide films 2A, 2B have a film thickness of, for example, 400 nm and a width set to be larger in the LOCOS oxide film indicated by the reference numeral 2A than that in the LOCOS oxide film indicated by the reference numeral 2B. Subsequently, thin oxide films 3A, 3B having a thickness of about 16 nm are formed on the surface of the silicon substrate 1. Then, a polysilicon film doped with phosphorous is formed on the whole surface to have a thickness of, for example, 300 nm, upon which a gate polysilicon electrode 4 is patterned by using a photolithography technique or a dry: etching technique.
Subsequently, as shown in FIG. 6B, a N channel element formation region is exposed to form a NMOS transistor, and then a resist mask 5A covering the P channel element formation region is patterned. Thereafter, boron (B) is ion-implanted through the LOCOS oxide film 2A, 2B and the gate polysilicon electrode 4 thereby to form a P well.
Next, as shown in FIG. 6C, boron (B) is similarly ion-implanted through the LOCOS oxide film 2A, 2B and the gate polysilicon electrode 4 thereby forming a N channel stop 7. Further, ion implantation of boron (B) for V.sub.th control is similarly made by using the resist mask 5A thereby forming a V.sub.th control layer 8 as shown in FIG. 7A.
Thus, in the above technique, the P well 6, the N channel stop 7 and the Vth control layer 8 are successively formed under ion implantation conditions by using the common resist mask 5A. It is to be noted that the above-discussed three ion implantations may be made before the film formation of the gate polysilicon electrode 4.
Thereafter, as shown in FIG. 7B, the resist mask 5A is stripped, and then a new resist mask 5B is patterned. This resist mask 5B is set to allow the P channel element formation region to be exposed while covering the N channel element formation region. Then, phosphorous (P) is ion-implanted upon using this resist mask 5B thereby forming a N well 9.
Subsequently, as shown in FIG. 7C, phosphorous (P) is ion-implanted to form a P channel stop layer 10. Further, ion-implantation of boron (B) for V.sub.th control is made through the gate polysilicon electrode 4 and the oxide film 3A, 3B thereby forming a V.sub.th control layer 11 as shown in FIG. 8A. It will be understood that the above three ion implantations for forming the N well 9, the P channel stop layer 10 and the V.sub.th control layer 11 may be made before the formation of the gate polysilicon electrode 4.
Next, after removing the resist mask 5B, a resist mask 5C is newly patterned to accomplish a high concentration ion implantation to the source and the drain of the N channel element formation region and the N well contact formation region as shown in FIG. 8B. Then, arsenic (As) is ion-implanted upon using the resist mask 5C thereby forming a source 12A, a drain 12B and a connected layer 13 at the side of the N well 9 as shown in FIG. 8(B). In this ion implantation, the gate polysilicon electrode 4 and the LOCOS oxide films 2A, 2B serve as a mask for ion implantation in the N channel formation region, while the LOCOS oxide films 2A, 2B surrounding the oxide film 3B serve as a mask for ion implantation in the N well contact region.
Subsequently, after the resist mask 5C is stripped, a resist mask 5D is patterned to accomplish a high concentration ion implantation to the source and the drain of the P channel element formation region and the P well contact formation region of the P well 6 as shown in FIG. 8C. Boron difluoride is ion-implanted in high concentration upon using the resist mask 5D thereby forming a source 14A and a drain 14B in the P channel element formation region and a connected layer 15 in the P well contact formation region. In this ion implantation, the gate polysilicon electrode 4 and the LOCOS oxide films 2A, 2B serve as a mask for the ion implantation in the P channel element formation region, while the LOCOS oxide films 2A, 2B surrounding the oxide film 3B serve as a mask for the ion implantation in the P well contact formation region.
Thus, as discussed above, in the semiconductor device production method, the resist masks 5A, 5B, 5C and 5D are required to be patterned in order to form a variety of impurity diffusion layers in the N channel element formation region and the P channel element formation region.
Now, in connection with semiconductor device production methods, a so-called oblique ion implantation has been proposed as disclosed in Japanese Patent Provisional Publications No. 5-6902 and 2-306624. The invention disclosed in Japanese Patent Provisional Publication No. 5-6902 is arranged such that resist masks having different widths are patterned through a clearance, upon which an oblique ion implantation is made in order to make a source and a drain as an asymmetrical impurity layer. The invention disclosed in Japanese Patent Provisional Publication No. 2-306624 is arranged such that an oblique ion implantation is made onto the inner wall surface of a connection opening for wiring which opening is formed in an insulated film thereby to damage the inner wall surface. A resultant damaged portion is intended to serve as an adsorption point for tungsten (W) in case of growing tungsten by using a CVD method.
However, drawbacks have been encountered in the above discussed semiconductor production methods. In the conventional production method as shown in FIGS. 6A to 8C, a common resist mask is used to accomplish the ion implantation for forming the well, the ion implantation for forming the channel stop layer and the ion implantation for forming the V.sub.th control layer, and therefore the number of steps for forming masks can be largely reduced. However, at least the ion implantation for forming the source and the drain is required to be accomplished upon using a resist mask which is different from that for the above ion implantations. Accordingly, in the process of forming a CMOS IC as discussed above, steps for forming at least four resist masks 5A, 5B, 5C, 5D are necessary to form the well, the channel stop layer, the V.sub.th control layer, the source drain, the well contact layer and the like.
In the invention disclosed in Japanese Patent Provisional Publication No. 5-6902, steps for forming a plurality of resist masks are necessary in a process for forming the source and the drain, so that a large number of masks are necessary for production of a CMOS IC. Additionally, the invention disclosed in Japanese Patent Provisional Publication No. 2-306624 is arranged to accomplish an ion implantation of argon (Ar) onto the: inner wall surface of the wiring connection opening and therefore is not arranged to form an impurity diffusion layer as a layer to be wired, at the bottom section of the connection opening for wiring. This does not serve to reduce the number of steps for forming resist masks.